Robert Oden

Dr. Robert Oden

Electrical and Computer Engineering

Engineering Building II

ECE 745 Application Specific Integrated Circuit Verification

3 Credit Hours

This course covers the verification process used in validating the functional correctness in today's complex Application Specific Integrated Circuits (ASICs). Topics include the fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verification problems to allow them to apply what they learn.


ASIC and FPGA Design with Verilog (NC State ECE 564)

Course Objectives

  1. To make the student proficient in the industry standard language used for functional verification, SystemVerilog.
  2. To give the student the ability to architect and implement layered, class based, simulation environments.
  3. To prepare the student for learning the industry standard methodology used for functional verification, UVM (Universal Verification Methodology).

Course Outcomes

  1. Students will be able to verify complex digital designs at block and chip level, identifying the contained bugs, and closing functional coverage, using SystemVerilog.
  2. Students will understand the purpose and design of base class packages used in functional verification.
  3. Students will demonstrate an understanding of layered test benches used in ASIC (Application-Specific Integrated Circuit) and FPGA (Field-Programmable Gate Array) Verification and their implementation using SystemVerilog.

Course Requirements

The course approach is similar to how the instructor teaches SystemVerilog to engineering professionals.  All instructional material will be delivered during lectures.  Lecture materials will include conceptual descriptions, examples, and sample code.  Questions during lectures is recommended and encouraged.  Instructional flow reflects typical verification development flow for production designs.

The course contains four (4) projects.  The projects build upon each other.  The content created in the first project will be used in the second project.  The content created in the second project will be used in the third project.  The content used in the third project will be used in the fourth project.   All concepts required for project development will be covered during lectures.  Students will have approximately four weeks to complete each project.  Projects will be done individually.  Projects will reflect architectures and techniques typically used for ASIC and FPGA verification of production designs.

The course contains three (3) tests.  The first test will be held in week 4 or soon thereafter.  The second test will be held in week 8 or soon thereafter. Test questions reflect typical interview questions on SystemVerilog.  Therefore, tests are closed book and closed-notes.

The audit requirement is to complete the first project and tests to a B standard or better.

ECE 745 Student Evaluation

Item  Contribution
Test1   10%
Test 2   10%
Test 3   10%
Project 1   15%
Project 2   25%
Project 3   15%
Project 4   15%
Total  100%


SystemVerilog for Verification – A Guide to Learning the Testbench Features, Chris Spear, Greg Tumbush Springer, 2012.

ISBN 978-1-4614-0714-0, e-ISBN 978-1-4614-0715-7


Updated 10/31/2022