Dr. Rhett Davis
Electrical and Computer Engineering
ECE 720 Electronic System Level and Physical Design
3 Credit Hours
Study of transaction-level modeling of digital systems-on-chip using SystemC. Simulation and analysis of performance in systems with distributed control. Synthesis of digital hardware from high-level descriptions. Physical design methodologies, including placement, routing, clock-tree insertion, timing, and power analysis. Significant project to design a core at system and physical levels. Prerequisites: knowledge of Object-Oriented Programming with C++ and Register-Transfer-Level design with Verilog or VHDL.
ECE 520 Digital ASIC Design.
By the end of the course, the students will be able to:
- Capture digital designs at the Transaction-Level and Electronic-System-Level of abstraction using SystemC
- Determine through simulation the performance of a system that includes embedded micro-processors, Dynamic Random Access Memory, Buses, and Direct Memory Access Controlers.
- Identify whether or not a SystemC description successfully models the behavior of a system
- Use behavioral synthesis tools to determine the hardware implied by a portion of C++ code
- Be able to execute a physical design and verification flow through the following steps:
◦ Clock-Tree Synthesis
◦ Repeater Insertion
◦ Static Timing Analysis
◦ Power Analysis
◦ Signal Integrity Analysis
◦ Power Grid Analysis
◦ Write simple Python scripts to analyze the output of ESL simulations and automate physical design tasks
10 Homework assignments (50%)
Design Project (50%)
No textbook required.
Computer and Internet Requirements
Students will need a relatively fast internet connection, because most of the work will be done using Linux remote-access through the Virtual Computing Laboratory, using X-Windows hosting software, such as X-Win32, which students can get from NCSU at no cost. If students have an internet connection that is fast enough to stream video lectures, then it should be sufficient.